DDR3/3L/2/LPDDR3/2

芯動(dòng)DDR3/3L/2/LPDDR3/2 Combo IP可(kě)提供支持JEDEC标準、兼容SDRAM設備的一站(zhàn)式交鑰匙解決方案，低功耗、高速率、小尺寸、時序優化。支持市場上所有的 JEDECDDR3/3L/2/LPDDR3/2 SDRAM組件。PHY組件包含DDR專用功能和(hé)實用高性能I/O、關(guān)鍵時序同步模塊 (TSM) 和(hé)低功耗/抖動(dòng)DLL，可(kě)對任何SDRAM接口進行可(kě)編程細粒度控制。且PHY都預先組裝了.lib、LEF和(hé)GDS，DDRn總線寬度可(kě)以從4位到72位或更多，易于集成，縮短(duǎn)客戶設計周期。該方案包括Controller和(hé)PHY，支持LPDDR3/2，可(kě)配置時序、驅動(dòng)強度參數和(hé)各種SDRAM接口，靈活高效。

The INNOSILICON DDR IPTM Mixed-Signal DDR3/3L/2/LPDDR3/2 Combo PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC DDR3/3L/2/LPDDR3/2 SDRAM components in the market. The PHY components contain LPDDR specialized functional and utility high performance I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.

The combo PHY solution includes DDRn controller and PHY, supporting DDR3/3L/2/LPDDR3/2. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.

KEY FEATURES:

Max data rate: 2133Mbps (DDR3/3L), 1333Mbps (DDR2/LPDDR2) and 1600Mbps (LPDDR3) respectively
x16/x32/x64 data path interface extendable
1.2V/1.35V/1.5V/1.8V JEDEC IO standard, support 1.2V POD_12 and 1.35V/1.5V/1.8V SSTL I/Os
Multiple drive strengths adjustable
Independent read and write timing adjustments with auto calibration
Low latency with programmable timings for secure data handling
Per bit deskew support
Supports point to point memory sub systems and multi-rank
PVT compensation and timing calibration for all corner reliability
At speed BIST, scan insertion
Various power-down modes for low power including self-refresh support
Low jitter with superior noise rejection
APB Port register access interface
Dual Row IO implementation and more
Supports both wire-bond and flip- chip packaging
Wire-bond speed is package limited
Support different DDRn type signal mapping for feasible PCB layout
Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market
Zero risk with robust ESD architecture
Maintains self-refresh I/O drive state during VDD power down
Extensive EDA tool support for various design automation flows
Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
DFI2.1/3.1 compliant memory controller interface
Flexible pad ring configuration to adapt for various design and chip scenarios
Integration with other INNOSILICON interface IP
Takes full advantage of process power savings and speed capability
Best in class low noise design to ensure best timing margin and signal integrity
DFT functions to reduce test time and ensure high test coverage
Several programmable PHY operating modes through simple register interface
Per Bit De-skew to improve composite data eye during read cycles at high speed

INNOSILICON ADVANTAGES:

Fully customized solutions including Controller and PHY
Over 500,000 wafers shipped out with Innosilicon DDRn/LPDDRn IP
All major processes fully covered, such as 110nm, 55nm to 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm.
Full harden PHY proven by 100+ tapeouts
Simple integration with pre-assembled PHY
Low IO pin count
High performance
Test chip and FPGA integration services available

EXAMPLE APPLICATIONS:

一鍵啟動(dòng)，簡化您的下(xià)一個(gè)産品設計流程！

輸入您的IP需求